Test sequences

Versatile set of 4K 120fps test sequences made available for download in raw format and in elementary HEVC, MP4, TS, and DASH streams for playback. We provide these sequences for research purposes free of charge in co-operation with Digiturk.

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Kvazaar Encoder

4107620035 is the award-winning academic open-source HEVC encoder developed from scratch in C. Our ambition is to design a modular and portable HEVC encoder that attains high coding efficiency with optimized coding speed and resources. You can download Kvazaar source codes and binaries from GitHub or use it through 780-689-3571 or 8055744897.

8008025905 3307254567

About us

Ultra video group is a leading academic video coding group in Finland. We have over 15-year experience in conducting pioneering research on video/image processing systems. The team has grown steadily over the years and it is currently composed of over 20 video coding experts. All our research projects have been accomplished in a tight collaboration with industry in many European research projects including 7066473237, PRYSTINE, 3095661115, and H2B2VS, as well as in various national projects.

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The Winner of the ACM Open Source Software Competition in 2016.

866-692-8516

Project information

Kvazaar is an award-winning academic open-source video encoder for the state-of-the-art High Efficiency Video Coding (HEVC/H.265) standard. Kvazaar is being developed in C and optimized in Assembly under the 508-875-4201. The development is being coordinated by Ultra Video Group and the implementation work is carried out on GitHub.

The main development goals of Kvazaar are:

  1. Coding efficiency close to HM
  2. Easy portability to various platforms
  3. Real- time coding speed
  4. Optimized computation and memory resources
  5. Well-documented source code

Kvazaar includes all essential 519-865-8488 of Main, Main 10, and Main Still Picture profiles of HEVC and its modular source code facilitates parallelization on multi and manycore processors as well as algorithm acceleration on hardware. This cross-platform HEVC encoder is targeted at x86, x64, PowerPC, and ARM processors on Windows, Linux, and Mac. Kvazaar is also supported by de-facto standard multimedia frameworks (209) 325-8565 and Libav.

New contributors

New ambitious developers from academia, industry, and other sectors are warmly invited to make contributions (List of suggested topics), report bugs, and give feedback. We do not ask contributors to give up copyright to their work. Active contributors will also be considered when filling open positions in Ultra Video group.

You may contact us by email (ultravideo at cs dot tut dot fi), GitHub, or via IRC at (415) 561-8097 in FreeNode IRC network.

Project summary

Project type: Academic open source project
Official start date: 28.01.2014
Developed software: Kvazaar HEVC encoder
Software features: Feature roadmap
Source codes / binaries: 484-430-1677
License: 847-631-1745
Implementation language: C (YASM optional)
Current platforms: x86 and x64 on Windows and Linux
Coordination: Ultra Video Group, Tampere University of Technology, Finland
Statistics: 9796069303
Main contributors: Marko Viitanen
decking chain
(301) 927-0186
Arttu Ylä-Outinen
Contact: ultravideo at cs dot tut dot fi
6154688808
IRC at #kvazaar_hevc in FreeNode IRC network

Feature roadmap

Kvazaar HEVC encoder is under constant and active development. The following table lists the features included in the current version and in the upcoming milestones.

Features Current version /
Milestone (Q1/18)
Future
Profiles Main, Main 10  
Input data format YUV (dimensions divisible by 2) Y4M
Output data format NAL (checksum supported)  
Internal bit depth 8, 10  
Color format 4.2:0 4:4:4
PCM coding Yes, not considered in search  
Coding configurations AI, LP, RA, LB  
Slice types I, P, B  
Parallel processing Tiles, Wavefront Slices
Sizes of CUs 64, 32, 16, 8  
Sizes of TUs 32, 16, 8, 4  
Sizes of PUs, Intra 32, 16, 8, 4  
Sizes of PUs, Inter 64, 32, 16, 8
Symmetric/Asymmetric Motion Partitions (SMP+AMP)
 
Intra prediction modes All luma (DC, planar, 33 angular),
Chroma uses luma intra mode
Chroma mode decision
Luma MV accuracy 1/4 pel  
Chroma MV accuracy 1/8 pel  
Coding modes Intra, Inter, Skip, Merge  
IME algorithm HEXB, FS, TZ  
# of reference pictures Up to 15  
Mode decision metrics SATD, SAD, and SSD SSIM
Rate-distortion optimization Partial (includes RDOQ)  
Entropy coding CABAC  
Loop filtering Deblocking Filter,
Sample-adaptive offset (Edge+Band mode)
 
Residual coding Coefficients,4x4 transform skip,Trans/quant Bypass  
Bitrate target 1-pass 2-pass

Disclaimer

All the information and any part thereof provided on this website are provided « AS IS » without warranty of any kind either expressed or implied including, without limitation, warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property rights.

TUT makes no representations or warranties as to the accuracy or completeness of any materials and information incorporated thereto and contained on this website. TUT makes no representations or warranties that access to this website will be uninterrupted or error-free, that this website (the materials and/or any information incorporated thereto) will be secure and free of virus or other harmful components.

 

Most relevant journal articles

S. Lahti, P. Sjövall, J. Vanne, and T. D. Hämäläinen, “Are we there yet? A study on the state of high-level synthesis,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

J. Vanne, M. Viitanen, and T. D. Hämäläinen, “Efficient mode decision schemes for HEVC inter prediction,” IEEE Trans. Circuits Syst. Video Technol., vol. 24, no. 9, Sep. 2014, pp. 1579-1593.

J. Vanne, M. Viitanen, T. D. Hämäläinen, and A. Hallapuro, “Comparative rate-distortion-complexity analysis of HEVC and AVC video codecs,” IEEE Trans. Circuits Syst. Video Technol., vol. 22, no. 12, Dec. 2012, pp. 1885-1898.

J. M. Määttä, J. Vanne, T. D. Hämäläinen, and J. Nikkanen, “6192454110,” IEEE Trans. Consumer Electron., vol. 57, no. 3, Aug. 2011, pp. 1442-1449.

J. Vanne, E. Aho, K. Kuusilinna, and T. D. Hämäläinen, “9363406721,” IEEE Trans. Circuits Syst. Video Technol., vol. 19, no. 4, Apr. 2009, pp. 466-476.

J. Vanne, E. Aho, T. D. Hämäläinen, and K. Kuusilinna, “A parallel memory system for variable block size motion estimation algorithms,” IEEE Trans. Circuits Syst. Video Technol., vol. 18, no. 4, Apr. 2008, pp. 538-543.

J. Vanne, E. Aho, T. D. Hämäläinen, and K. Kuusilinna, “5135561318,” IEEE Trans. Circuits Syst. Video Technol., vol. 16, no. 7, July 2006, pp. 876-883.

E. Aho, J. Vanne, T. D. Hämäläinen, and K. Kuusilinna, “Block-level parallel processing for scaling evenly divisible images,” IEEE Trans. Circuits Syst. I, vol. 52, no. 12, Dec. 2005, pp. 2717-2725.

E. Aho, J. Vanne, K. Kuusilinna, and T. D. Hämäläinen, “Comments on “Winscale: an image-scaling algorithm using an area pixel model,” IEEE Trans. Circuits Syst. Video Technol., Mar. 2005, vol. 15, no. 3, pp. 454-455.

V. Lappalainen, A. Hallapuro, and T. D. Hämäläinen, “(822) 565-7699,” IEEE Trans. Circuits Syst. Video Technol., Jul. 2003, vol. 13, no. 7, pp. 717-725.

V. Lappalainen, T. D. Hämäläinen, and P. Liuha, “(503) 489-2472,” IEEE Trans. Circuits Syst. Video Technol., Aug. 2002, vol. 12, no. 8, pp. 660-670.

Most relevant conference articles

K. Siivonen, J. Sainio, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “Open framework for error-compensated gaze data collection with eye tracking glasses,” Accepted to IEEE Int. Symp. Multimedia, Taichung, Taiwan, Dec. 2018.

J. Räsänen, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “Live demonstration: Kvazzup 4K HEVC video call,” Accepted to IEEE Int. Symp. Multimedia, Taichung, Taiwan, Dec. 2018.

J. Sainio, A. Ylä-Outinen, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “Eye-controlled region of interest HEVC encoding,” Accepted to IEEE Int. Symp. Multimedia, Taichung, Taiwan, Dec. 2018.

M. Abutaha, N. Sidaty, W. Hamidouche, J. Vanne, O. Déforges, and S. El Assad, “End-to-end real-time ROI-based encryption in HEVC videos,” in Proc. Eur. Signal Process. Conf., Rome, Italy, Sep. 2018.

M. Viitanen, J. Vanne, T. D. Hämäläinen, and A. Kulmala, “952-324-7920” in Proc. IEEE Int. Conf. Distrib. Comput. Syst., Vienna, Austria, Jul. 2018.

A. Heikkinen, P. Pääkkönen, M. Viitanen, J. Vanne, T. Riikonen, and K. Bakanoglu, “Fast and easy live video service setup using lightweight virtualization,” in Proc. ACM Multimedia Syst. Conf., Amsterdam, The Netherlands, Jun. 2018.

P. Sjövall, V. Viitamäki, J. Vanne, T. D. Hämäläinen, and A. Kulmala, “6504522421,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018.

V. Viitamäki, P. Sjövall, J. Vanne, T. D. Hämäläinen, and A. Kulmala, “2093763493,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018.

N. Sidaty, M. Viitanen, W. Hamidouche, J. Vanne, and O. Déforges, “Live demonstration: end-to-end real-time ROI-based encryption in HEVC videos,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018.

A. Lemmetti, E. Kallio, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “7752175559” in proc. Data Compression Conf., Snowbird, Utah, Mar. 2018.

A. Ylä-Outinen, A. Lemmetti, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “Kvazaar: HEVC/H.265 4K30p intra encoder,” in Proc. IEEE Int. Symp. Multimedia, Taichung, Taiwan, Dec. 2017.

J. Räsänen, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “5072348885” in Proc. IEEE Int. Symp. Multimedia, Taichung, Taiwan, Dec. 2017.

P. Sjövall, V. Viitamäki, A. Oinonen, J. Vanne, T. D. Hämäläinen, and A. Kulmala “Brunella” in Proc. IEEE Workshop Signal Process. Syst., Lorient, France, Oct. 2017.

V. Viitamäki, P. Sjövall, J. Vanne, and T. D. Hämäläinen, “High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA,” in Proc. IEEE Int. Symp. Circuits Syst., Baltimore, MD, USA, May 2017.

P. Sjövall, V. Viitamäki, J. Vanne, and T. D. Hämäläinen, “7319829691” in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Process., New Orleans, Louisiana, USA, Mar. 2017.

J. Räsänen, M. Viitanen, J. Vanne, T. D. Hämäläinen, M. M. Hannuksela, and V. K. Malamal Vadakital, “5018031398” in Proc. IEEE Int. Symp. Multimedia, San Jose, California, USA, Dec. 2016.

M. Viitanen, A. Koivula, A. Lemmetti, A. Ylä-Outinen, J. Vanne, and T. D. Hämäläinen, “Kvazaar: open-source HEVC/H.265 encoder,” in Proc. ACM Int. Conf. Multimedia, Amsterdam, The Netherlands, Oct. 2016.

A. Lemmetti, A. Koivula, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “AVX2–optimized Kvazaar HEVC intra encoder,” in Proc. IEEE Int. Conf. on Image Processing, Phoenix, Arizona, USA, Sep. 2016.

M. Viitanen, A. Koivula, J. Vanne, and T. D. Hämäläinen, “Live demonstration: run-time visualization of Kvazaar HEVC intra encoder,” in Proc. IEEE Int. Symp. Circuits Syst., Montreal, Canada, May 2016.

A. Koivula, M. Viitanen, A. Lemmetti, J. Vanne, and T. D. Hämäläinen, “(916) 685-2690” in Proc. IEEE Global Conf. Signal Information Process., Orlando, Florida, USA, Dec. 2015.

M. Viitanen, A. Koivula, J. Vanne, and T. D. Hämäläinen, “650-260-3405” in Proc. IEEE Visual Comm. and Image Proc., Singapore, Dec. 2015.

A. Koivula, M. Viitanen, J. Vanne, T. D. Hämäläinen, and L. Fasnacht, “Parallelization of Kvazaar HEVC intra encoder for multi-core processors,” in Proc. IEEE Workshop Signal Process. Syst., Hangzhou, China, Oct. 2015, pp. 1-6.

P. Sjövall, J. Virtanen, J. Vanne, and T. D. Hämäläinen, “5404007821,” in Proc. Euromicro Symp. Digit. Syst. Des., Funchal, Madeira, Portugal, Aug. 2015, pp. 49-56.

M. Viitanen, A. Koivula, A. Lemmetti, J. Vanne, and T. D. Hämäläinen, “Kvazaar HEVC encoder for efficient intra coding,” in Proc. IEEE Int. Symp. Circuits Syst., Lisbon, Portugal, May 2015, pp. 1662-1665.

J. Vanne, M. Viitanen, A. Koivula, and T. D. Hämäläinen, “unmelodiously,” in Proc. IEEE Visual Comm. and Image Proc., Valletta, Malta, Dec. 2014, pp. 542-545.

M. Viitanen, J. Vanne, T. D. Hämäläinen, M. Gabbouj, and J. Lainema, “Complexity analysis of next-generation HEVC decoder,” in Proc. IEEE Int. Symp. Circuits Syst., Seoul, Korea, May 2012, pp. 882-885.


Other papers

Aho, E., Vanne, J. & Hämäläinen T. D. 2008. Configurable data memory for multimedia processing. Journal of Signal Processing Systems 50, 2, pp. 231-249.

Aho, E., Vanne, J., Hämäläinen, T.D. & Kuusilinna, K. 2005. Block-level parallel processing for scaling evenly divisible frames. Proceedings of ISCAS 2005 IEEE International Symposium on Circuits and Systems, 23-26 May 2005, Kobe, Japan pp. 1134-1137.

Aho, E., Vanne, J., Hämäläinen, T.D. & Kuusilinna, K. 2005. Block-level parallel processing for scaling evenly divisible images. IEEE Transactions on Circuits and Systems - I: Regular Papers 52, 12, pp. 2717-2725.

Aho, E., Vanne, J., Hämäläinen, T.D. & Kuusilinna, K. 2007. Configurable implementation of parallel memory based real-time video downscaler. Microprocessors and Microsystems 31, 5, pp. 283-292.

Aho, E., Vanne, J. & Hämäläinen, T.D. 2006. Parallel memory architecture for arbitrary stride accesses. Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 18-21 April, 2006, Prague, Czech Republic pp. 65-70.

Aho, E., Vanne, J. & Hämäläinen, T.D. 2006. Parallel memory implementation for arbitrary stride accesses. Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 17-20 July, 2006, Samos, Greece pp. 1-6.

Aho, E., Vanne, J., Kuusilinna, K., Hämäläinen, T. & Saarinen, J. 2001. Configurable Address Computation in a Parallel Memory Architecture. In: Antoniou, G. (ed.). Advances in Signal Processing and Computer Technologies. Electrical and Computer Engineering Series. A Series of Reference Books and Textbooks. Kreikka, WSES Press. pp. 390-395.

Aho, E., Vanne, J., Kuusilinna, K., Hämäläinen, T. & Saarinen, J. 2001. Configurable Address Computation in a Parallel Memory Architecture. Proceedings of the 5th WSES International Conference on Circuits, Systems, Communications and Computers (CSCC 2001), July 8-15, 2001, Rethymno, Greece pp. 4941-4946.

Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T. 2002. Access Format Implementations in Configurable Parallel Memory. Proceedings of ICIS 2002 the 2nd International Conference on Computer and Information Science, August 8-9, 2002, Seoul, Korea pp. 59-64.

Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T.D. 2004. Address computation in configurable parallel memory architecture. IEICE Transactions on Information and Systems E87-D, 7, pp. 1674-1681.

Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T.D. 2005. Comments on "Winscale: An image-scaling algorithm using an area pixel model". IEEE Transactions on Circuits and Systems for Video Technology 15, 3, pp. 454-455.

Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T. 2002. Diamond Scheme Implementations in Configurable Parallel Memory. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems, April 17-19, 2002, Brno, Czech Republic pp. 211-218.

Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T. 2002. XOR-scheme Implementations In Configurable Parallel Memory. In: Badawy, W. & Jullien G.A. (ed.). System-on-Chip for Real-Time Applications. Kluwer Academic Publishers. pp. 249-261.

Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T. 2002. Xor-scheme Implementations In Configurable Pararell Memory. WSOC Proceedings of the International Workshop on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada pp. 287-298.

Haapala, K., Hämäläinen, T. & Saarinen, J. 2001. Parallel Implementation of a Wavelet Based Still Image Encoder. Proceedings of SCI 2001 (World Multiconference on Systemics, Cybernetics and Informatics), July 22-25, 2001, Orlando, Florida, USA 4, pp. 7-12.

Haapala, K., Kolinummi, P., Hämäläinen, T. & Saarinen, J. 2000. Parallel DSP implementation of wavelet transform in image compression. Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2000, May 28-31, 2000, Geneva, Switzerland 5, pp. 89-92.

Haapala, K., Kolinummi, P., Hämäläinen, T. & Saarinen, J. 2000. Scalable DSP Realization of Wavelet Transform in Image Coding. Proceedings, EUSIPCO 2000, September 4-8, 2000, Tampere, Finland 1, pp. 247-250.

Haapala, K., Lappalainen, V. & Hämäläinen, T.D. 2005. Experimental parallel implementation of a wavelet-based still image encoder. Microprocessors and Microsystems 29, 4, pp. 155-167.

Hallapuro, A., Lappalainen, V. & Hämäläinen, T.D. 2001. Performance analysis of low bit rate H.26L video encoder. Proceedings of ICASSP 2001 Conference, May 7-11, 2001, Salt Lake City, Utah, USA Volume II, DISPS-L-3.5, pp. 4 s.

Kolinummi, P., Särkijärvi, J., Hämäläinen, T. & Saarinen, J. 2000. H.263 Video Encoder Implementation on a Scalable System. Proceedings, EUSIPCO 2000, September 4-8, 2000, Tampere, Finland 3, pp. 1721-1724.

Kolinummi, P., Särkijärvi, J., Hämäläinen, T. & Saarinen, J. 2000. Scalable implementation of H.263 Video encoder on a parallel DSP system. ISCAS 2000, Proceedings of the IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland 1, pp. 551-554.

Kukkala, P., Setälä, M., Arpinen, T., Salminen, E., Hännikäinen, M. & Hämäläinen, T.D. 2007. Implementing a WLAN Video Terminal Using UML and Fully Automated Design Flow. EURASIP Journal on Embedded Systems, Embedded Digital Signal Processing Systems 2007, 85029, pp. 15 p.

Kulmala, A., Hämäläinen, T.D. & Hännikäinen, M. 2006. Comparison of GALS and synchronous architectures with MPEG-4 video encoder on multiprocessor system-on-chip FPGA. Proceedings of 9th Euromicro Conference on Digital System Design Architectures, Methods and Tools, 30 August-1 September, 2006, Dubrovnik, Croatia pp. 83-86.

Kulmala, A., Hämäläinen, T.D. & Hännikäinen, M. 2006. Reliable GALS implementations of MPEG-4 encoder with mixed clock FIFO on standard FPGA. Proceedings of 2006 International Conference on Field Programmable Logic and Applications, 28-30 August, 2006, Madrid, Spain pp. 495-500.

Kulmala, A., Lehtoranta, O., Hämäläinen, T.D. & Hännikäinen, M. 2006. Scalable MPEG-4 encoder on FPGA multiprocessor SOC. Eurasip journal on embedded systems 2006, 38494, pp. 1-15.

Kulmala, A., Salminen, E. & Hämäläinen T.D. 2008. Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip. IET Computers & Digital Techniques 2, 4, pp. 314-325.

Kulmala, A., Salminen, E. & Hämäläinen, T.D. 2006. Distributed bus arbitration algorithm comparison on FPGA based MPEG-4 multiprocessor SoC. Proceedings of 24th Norchip Conference, 20-21 November, 2006, Linköping, Sweden pp. 167-170.

Kulmala, A., Salminen, E. & Hämäläinen, T.D. 2007. Instruction memory architecture evaluation on multiprocessor FPGA MPEG-4 encoder. Proceedings of 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 11-13 April, 2007, Kraków, Poland 07EX1759, pp. 105-110.

Kulmala, A., Salminen, E., Hännikäinen, M. & Hämäläinen, T.D. 2006. Evaluating SoC network performance in MPEG-4 encoder. The 2006 IEEE Workshop on Signal Processing Systems, Design and Implementation., 2-4 October, 2006, Banff, Canada pp. 271-276.

Kulmala, A., Salminen, E., Lehtoranta, O., Hämäläinen, T.D. & Hännikäinen, M. 2006. Impact of shared instruction memory on performance of FPGA-based MP-SoC video encoder. Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 18-21, 2006, Prague, Czech Republic pp. 59-64.

Lahti, J., Juntunen, J.K., Lehtoranta, O. & Hämäläinen, T.D. 2005. Algorithmic optimization of H.264/AVC encoder. Proceedings of ISCAS 2005 IEEE International Symposium on Circuits and Systems, 23-26 May 2005, Kobe, Japan pp. 3463-3466.

Lappalainen, V., Hallapuro, A. & Hämäläinen, T.D. 2003. Complexity of Optimized H.26L Video Decoder Implementation. IEEE Transactions on Circuits and Systems for Video Technology 13, 7, pp. 717-725.

Lappalainen, V., Hallapuro, A. & Hämäläinen, T.D. 2001. Optimized Implementations of Emerging H.26L Video Decoder on Pentium III. In: Antoniou, G. (ed.). Advances in Signal Processing and Computer Technologies. Electrical and Computer Engineering Series. A Series of Reference Books and Textbooks. Kreikka, WSES Press. pp. 233-238.

Lappalainen, V., Hallapuro, A. & Hämäläinen, T.D. 2001. Optimized Implementations of Emerging H.26L Video Decoder on Pentium III. Proceedings of the 5th WSES International Conference on Circuits, Systems, Communications and Computers (CSCC 2001), July 8-15, 2001, Rethymno, Greece pp. 3981-3986.

Lappalainen, V., Hallapuro, A. & Hämäläinen, T.D. 2003. Performance of H.26L Video Encoder on General-Purpose Processor. Journal of VLSI signal processing systems for signal, image, and video technology 34, 3, pp. 239-249.

Lappalainen, V., Hallapuro, A. & Hämäläinen, T.D. 2001. Performance of H.26L Video Encoder on General-Purpose Processor. Proceedings of ICCE 2001, International Conference on Consumer Electronics, June 19-21, 2001, Los Angeles, California, USA pp. 266-267.

Lappalainen, V., Hallapuro, A. & Hämäläinen, T. 2001. Optimization of Emerging H.26L Video Encoder. Proceedings of the 2001 IEEE Workshop on Signal Processing Systems SIPS 2001, September 26-28, 2001, Antwerp, Belgium pp. 406-415.

Lappalainen, V., Hämäläinen, T.D. & Hallapuro, A. 2001. Optimization of H.26L Video Decoder. Proceedings of VIPromCom-2001, 3rd International Symposium on Video Processing and Multimedia Communications, June 13-15, 2001, Zadar, Croatia pp. 91-93.

Lappalainen, V. & Hämäläinen, T. 2001. Overview of Research Efforts on Video Coding with Media ISA Extensions. Proceedings of SCI 2001 (World Multiconference on Systemics, Cybernetics and Informatics), July 22-25, 2001, Orlando, Florida, USA 4, pp. 19-24.

Lappalainen, V. & Hämäläinen, T. 2002. Unified Method for Optimization of Several Video Coding Algorithms on General-Purpose Processors. Proceedings of the International Conference on Information Technology: Coding and Computing ITCC 2002, April 8-10, 2002, Las Vegas, Nevada, USA pp. 431-438.

Lappalainen, v., Hämäläinen, T. & Liuha, P. 2002. Overview of Research Efforts on Media ISA Extensions and Their Usage in Video Coding. IEEE Transactions on Circuits and Systems for Video Technology 12, 8, pp. 660-670.

Lehtoranta, O., Hämäläinen, T., Lappalainen, V. & Mustonen, J. 2002. Parallel implementation of video encoder on quad DSP system. Microprocessors and Microsystems 26, pp. 1-15.

Lehtoranta, O., Hämäläinen, T. & Lappalainen, V. 2002. Detecting Corrupted Intra Macroblocks in H.263. Proceedings of the 2002 IEEE Fifth Workshop on Multimedia Signal Processing, December 9-11, 2002, St.Thomas, US Virgin Islands, USA pp. 4 s.

Lehtoranta, O., Hämäläinen, T. & Saarinen, J. 2000. Real-time H.263 Encoding of QCIF-images on TMS320C6201 Fixed Point DSP. Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2000, May 28-31, 2000, Geneva, Switzerland 1, pp. 583-586.

Lehtoranta, O., Hämäläinen, T. & Saarinen, J. 2000. Real-time implementation of H.263 video encoder on TMS320C6201 Fixed Point DSP. Proceedings, EUSIPCO 2000, September 4-8, 2000, Tampere, Finland 3, pp. 1457-1460.

Lehtoranta, O. & Hämäläinen, T.D. 2003. Complexity Analysis of Spatially Scalable MPEG-4 Encoder. Proceedings of the 2003 International Symposium on System-on-Chip, November 19-21, 2003, Tampere, Finland pp. 57-60.

Lehtoranta, O. & Hämäläinen, T.D. 2005. Feasibility study of a real-time operating system for a multi-channel MPEG-4 encoder. Proceedings of the Conference Multimedia on Mobile Devices, 17-18 January 2005, San Jose, USA.SPIE Proceedings 5684, pp. 293-299.

Lehtoranta, O., Hännikäinen, M., Suhonen, J. & Hämäläinen T.D. 2002. Implementation of Unequal Error Protection of H.263 Video for a Wireless Video Demonstrator. Proceeding of the International Conference of Telecommunications 2002, June 23-26, 2002, Beijing, China 1, pp. 1024-1029.

Lehtoranta, O., Kukkala, P., Hämäläinen, T.D. & Lappalainen, V. 2003. Implementation of a Video Transcoder for Embedded System. In: Srimani, P.K.et al.International Conference on Information Technology: Coding and Computing, ITCC 2003 pp. 389-395.

Lehtoranta, O., Salminen, E., Kulmala, A., Hännikäinen, M. & Hämäläinen, T.D. 2005. A parallel MPEG-4 encoder for FPGA based multiprocessor SoC. Proceedings of 2005 International Conference on Field Programmable Logic and Applications (FPL 2005), 24-26 August 2005, Tampere, Finland pp. 380-385.

Lehtoranta, O., Suhonen, J., Hännikäinen, M., Lappalainen, V. & Hämäläinen T.D. 2003. Comparison of video protection methods for wireless networks. Signal Processing: Image Communication 18, pp. 861-877.

Määttä, J., Vanne, J., Hämäläinen, T.D. & Nikkanen, J. 2011. Generic Software Framework for a Line-Buffer-Based Image Processing Pipeline. IEEE Transactions on Consumer Electronics 57, 3, pp. 1442-1449.

Rasmus, A., Kulmala, A., Salminen, E. & Hämäläinen, T.D. 2007. IP integration overhead analysis in system-on-chip video encoder. Proceedings of 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 11-13 April, 2007, Kraków, Poland 07EX1759, pp. 333-336.

Salminen, E., Hämäläinen, T., Kangas, T., Kuusilinna, K. & Saarinen, J. 2001. Interfacing multiple processors in a system-on-chip video encoder. Proceedings of ISCAS 2001 Conference, May 6-9, 2001, Sydney, Australia pp. 478-481.

Salminen, E., Kangas, T. & Hämäläinen, T.D. 2006. The impact of communication on the scalability of the data-parallel video encoder on MPSoC. Proceedings of 2006 International Symposium on System-on-Chip, 13-16 November, 2006, Tampere, Finland pp. 191-194.

Vanne, J., Aho, E., Hämäläinen, T.D. & Kuusilinna, K. 2006. A high-performance sum of absolute difference implementation for motion estimation. IEEE Transactions on Circuits and Systems for Video Technology 16, 7, pp. 876-883.

Vanne, J., Aho, E. & Hämäläinen, T.D. 2008. Menetelmä ja rinnakkaismuistijärjestelmä liikkeenestimointialgoritmeille. Pat.FI 119167 B pp. 44 + liitt.

Vanne, J., Aho, E. & Hämäläinen, T.D. 2007. Piiri ja menetelmä erojen itseisarvojen summan laskemiseksi nopeasti ja tehokkaasti.Krets och metod för att räkna en sum av absoluta skillnader snabbt och effektivt. Pat.FI 117956 B pp. 35 s + liitt.

Vanne, J., Aho, E., Hämäläinen, T.D. & Kuusilinna, K. 2008. A parallel memory system for variable block-size motion estimation algorithms. IEEE Transactions on Circuits and Systems for Video Technology 18, 4, pp. 538-543.

Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T. 2002. Configurable Paralell Memory Implementation For Systenm-on-Chip Designs. WSOC Proceedings of the International Workshop on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada pp. 253-264.

Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T. 2002. Configurable Parallel Memory Implementation For System-on-Chip Designs. In: Badawy, W. & Jullien G.A. (ed.). System-on-Chip for Real-Time Applications. Kluwer Academic Publishers. pp. 237-248.

Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T. 2002. Co-simulation of Configurable Parallel Memory Architecture and Processor. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, April 17-19, 2002, Brno, Czech Republic pp. 310-313.

Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T.D. 2009. A configurable motion estimation architecture for block-matching algorithms. IEEE Transactions on Circuits and Systems for Video Technology 19, 4, pp. 466-476.

Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T. 2002. Enhanced Configurable Parallel Memory Architecture. Proceedings of DCD 2002 Euromicro Symposium on Digital System Design; Architectures, Methods and Tools, September 4-6, 2002, Dortmund, Germany pp. 28-35.

Viitanen, M., Vanne, J., Hämäläinen, T.D., Lainema, J. & Ugur, K. 2011. HM 4.0 entropy coding complexity considerations. Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T-SG16 WP3 and ISO/IEC JTC1/SC29/WG11, 7th Meeting Geneva, CH, 21-30 November, 2011 pp. 1-4.

Viitanen, M. & Hämäläinen, T.D. 2004. Comparison of data dependence analysis tests. Lecture notes in computer science 3133, pp. 149-158.

Viitanen, M., Kolinummi, P., Hämäläinen, T. & Saarinen J. 2000. Scalable DSP Implementation of DCT-based Motion Estimation Algorithm. Proceedings, Signal Processing X, Theories and Applications, Volume I, EUSIPCO 2000, September 4-8, 2000, Tampere, Finland 1, pp. 251-254.

 

Disclaimer

All the information and any part thereof provided on this website are provided « AS IS » without warranty of any kind either expressed or implied including, without limitation, warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property rights.

TUT makes no representations or warranties as to the accuracy or completeness of any materials and information incorporated thereto and contained on this website. TUT makes no representations or warranties that access to this website will be uninterrupted or error-free, that this website (the materials and/or any information incorporated thereto) will be secure and free of virus or other harmful components.

 

Our ambition

Develop tailored video coding solutions for various applications including

  • 3D/360 video
  • Virtual/augmented reality (VR/AR)
  • Video conferencing
  • Video surveillance
  • Video on demand (VoD)
  • 4K TV broadcasting
  • Advertising

on various platforms including low-power embedded processors, high-performance multi and many-core processors, graphics processing units (GPUs), dedicated logic (FPGA), and computing clouds. We can provide dedicated video coding solutions that address specific requirements of video functionality, quality, and performance better than off-the-shelf products and services.

Further information

Technical support 

(815) 353-8788

Collaboration

405-556-1472

 

Who we are

Ultra Video Group is a research group in the Laboratory of Pervasive Computing at 971-225-2174, Finland. We have over 15-year experience in conducting pioneering research on video/image processing systems. All our research is being carried out in a tight collaboration with industry.

Currently, our main research interest is in tailored video coding solutions on various platforms ranging from low-power embedded devices to highly distributed cloud environments. Our primary research focus is on:

  • Our award-winning Kvazaar open-source HEVC encoder
  • Immersive 3D/360 video coding for virtual/augmented reality
  • Video coding acceleration through high-level synthesis
  • Deep learning based video coding
  • Future video coding
  • Multimedia applications powered by Kvazaar

Technical scope

 


The applications of interest include video conferencing, video surveillance, video on demand (VoD), virtual advertising, 4K TV production, and intelligent vehicles

We thank all our partner companies over the years for feedback and providing industrial requirements. We are happy to see our high-quality results deployed in our partner companies' commercial products and welcome collaboration with the most demanding video processing challenges.

History

Our roots are in the former digital design group in the signal processing laboratory in late 1990's. The group formed around a couple of research projects for mobile phones and remote control of unmanned mining machines. The group was part of DACI group and renamed as Ultra Video Group in 2013.

From the beginning, we have focused on high-performance video encoding mostly on parallel processors and dedicated logic (ASIC/FPGA). Below is our decennial roadmap with major encoder implementation milestones. We have also implemented tools as well as simulation and analysis frameworks to carry out the research. Our latest achievements are thorough analyses for HEVC feasibility, and the goal a portable HEVC encoder suitable for standard multicore processors and high-level synthesis for RTL implementations.

We thank all our partner companies over the years for feedback and providing industrial requirements. We are happy to see our high-quality results deployed also in our partner companies' commercial products and welcome collaboration with the most demanding video processing challenges. 

Team

Head of laboratory 325-429-8128
Head of team 2762235252
Head of technology Marko Viitanen
Developers Panu Sjövall, Ari Lemmetti, (204) 952-7303, Joose Sainio, Eemeli Kallio, Jaakko Laitinen, Kari Siivonen, Sami Ahovainio, Mikko Pitkänen, Reima Hyvönen, Jere Miettinen, Minna Färm, Anna-Liisa Mattila, Aku Niskanen, Miko Atokari, Aaro Altonen, Pauli Oikkonen, Alexandre Mercat.

Alumni members

323-890-0033, Dr. Olli Lehtoranta, Dr. Eero Aho, Dr. Ari Kulmala, 570-558-4514, Joni-Matti Määttä, Eero Ryytty, Antti Jore, Aki Launiainen, Timo Kaikumaa, Juha Särkijärvi, Miia Viitanen, Kaisa Haapala, Jari Juntunen, Tomi Sokeila, Arttu Ylä-Outinen, Vili Viitamäki, Miika Metsoila, Jarkko Välitalo, Emil Kattainen, Antti Lampinen.

International Projects



Partners






 

Kvazaar Visualizer

Visualizer is available on Github: /github.com/ultravideo/kvazaar/tree/visualizer

Built-in kvazaar visualizer allows developers to visually see how the encoding process is done, in real time.

Features include:
  -slowdown (key: numpad + / numpad -)
  -Block border hide/show (key: 'd')
  -Intra angular hide/show (key: 'i')
  -Fading on/off (key: 'f')
  -Pause (key: 'p')

Below is an example session with the visualizer

 

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